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El ascenso de RISC: 2025 será el año de la primera computadora portátil RISC-V casi convencional, como lo confirmó el CEO de Framework, pero no creo que esté lista para el horario de máxima audiencia.

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  • El proveedor de portátiles modulares Framework dijo que lanzará un producto RISC-V en 2025
  • RISC-V es el equivalente de hardware de Linux, es de código abierto y gratuito
  • Más empresas de tecnología están adoptando esta tecnología, pero aún tiene que llegar a la corriente principal de manera significativa.

Riesgo-V, y Código abierto ISA fue desarrollado en la Universidad de California, Berkeley en 2010, y ha ganado constantemente interés como una alternativa personalizable a los estándares ISA propietarios, como x86 y brazo.

Su enfoque sin licencia permite a los fabricantes crear y modificar procesadores sin restricciones, lo que lleva a su adopción en muchas aplicaciones especializadas, y este año podría marcar un paso importante hacia una adopción más amplia de esta arquitectura por parte de los consumidores.

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Algo que pone nerviosos a Arm, Intel y AMD; Nvidia, Qualcomm, Google y Samsung realizarán presentaciones centradas en IA en la Cumbre RISC-V

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el ultimo Cumbre RISC-V En Santa Clara, California, vio a los principales actores de la industria como NVIDIAqualcomm, Googley Samsung Ofrezca presentaciones centradas en la inteligencia artificial y el papel cada vez mayor de la arquitectura RISC-V.

La participación de actores de renombre ha puesto de relieve el creciente impulso detrás de RISC-V, que se considera cada vez más como un fuerte competidor de arquitecturas propietarias como brazo y x86.

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Meta muestra hardware que admitirá recomendaciones para Facebook e Instagram, con núcleos RISC-V de bajo costo y memoria LPDDR5 convencional que forman el núcleo de su conclusión de recomendaciones MTIA.

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Meta presentará la primera generación de su acelerador de inferencia de IA diseñado para impulsar los modelos de calificación y recomendación que son componentes centrales de Facebook e Instagram en 2023.

El chip Training and Inference Acceleration (MTIA), que puede manejar la inferencia pero no el entrenamiento, Actualizado en abrilSe duplicó el ancho de banda de computación y memoria de la primera solución.

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Samsung reveló accidentalmente planes para lanzar una CPU RISC-V: este podría ser el misterioso acelerador de IA MACH-1 que podría rivalizar con la GPU de la serie H de Nvidia

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Samsung Es posible que haya revelado accidentalmente que está desarrollando una CPU/acelerador RISC-V.

El error ocurrió durante una sesión titulada “Desbloqueando los próximos 35 años de software HPC e IA” en la reciente conferencia ISC, donde una diapositiva que hablaba de la Fundación UXL (Unified Accelerator Foundation) se refería a “La CPU/AI RISC-V de Samsung”. acelerador.”

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Puesta en marcha de una supercomputadora en un chip: una sola tarjeta PCIe tiene más de 6.000 núcleos RISC-V, con la capacidad de escalar a más de 360.000 núcleos, pero la puesta en marcha todavía está muy lejos en términos de precios.

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InspireSemi anunció la exitosa inauguración de su chip Thunderbird I Accelerated Computing para su fabricación en TSMC.

Este “clúster de supercomputadora en un chip” altamente diferenciado cuenta con 1.536 núcleos de CPU RISC-V de 64 bits dedicados, diseñados específicamente para computación científica de alto nivel y procesamiento de datos complejos.

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Firm headed by legendary chip architect behind AMD Zen finally releases first hardware — days after being selected to build the future of AI in Japan, Tenstorrent unveils Grayskull, its RISC-V answer to GPUs

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Tenstorrent, the firm led by legendary chip architect Jim Keller, the mastermind behind AMD‘s Zen architecture and Tesla’s original self-driving chip, has launched its first hardware. Grayskull is a RISC-V alternative to GPUs that is designed to be easier to program and scale, and reportedly excels at handling run-time sparsity and conditional computation.

Off the back of this, Tenstorrent has also unveiled its Grayskull-powered DevKits – the standard Grayskull e75 and the more powerful Grayskull e150. Both are inference-only hardware designed for AI development, and come with TT-Buda and TT-Metalium software. The former is for running models right away, while the latter is for users who want to customize their models or write new ones.

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Ventana Veyron V2 redefines data center efficiency with cutting-edge RISC-V processor

a picture of the Ventana Veyron V2 RISC-V Processor and Platform

Ventana Micro Systems as announced the introduction of its latest marvel in the Veyron lineup—the Veyron V2. Marketed as the highest performance RISC-V processor to date, it’s clear that Ventana has not only listened to its customer base but has also pushed the envelope in performance and efficiency. The Veyron V2, available as both chiplets and IP, is a testament to Ventana’s dedication to fostering rapid customer adoption through technological innovation.

40% Performance Gain

If you are wondering how Ventana has achieved this milestone, you will be pleased to know that a significant boost in the processor’s capabilities has been realized. With an impressive 40% surge in performance, the Veyron V2 is not just about speed; it’s about smarter, more efficient processing. This leap is attributed to a slew of microarchitecture enhancements, a state-of-the-art processor fabric architecture, and an expanded cache hierarchy, complete with a high-performance vector processor to top it off.

One can’t help but appreciate the strategic initiative known as RISE, which stands for RISC-V International Software Ecosystem. This program is instrumental in bolstering the support ecosystem, ensuring that Veyron V2 can swiftly roll out solutions that are open, scalable, and versatile.

From a business standpoint, the economic and temporal advantages are hard to ignore. Thanks to the industry-leading UCIe chiplet interconnect, Veyron V2 is not just a powerhouse but also a savvy economic choice. It offers a reduction in development costs by a staggering 75% and accelerates time to market by up to two years. It’s remarkable how chiplet-based solutions can provide such elasticity in computing, input/output, and memory configurations, allowing businesses to focus on their unique innovations and specialized workload optimizations.

In the realm of data centers, Ventana’s Domain Specific Accelerator technology works in concert with the Veyron V2 processor pipeline, enhancing efficiency across the board and fostering an environment ripe for customer-specific innovation. Industry experts, like Patrick Moorhead of Moor Insights & Strategy, believe that the cost-effective performance equation Ventana has achieved with the V2 chip may very well redefine benchmarks in high-performance computing.

Ventana Veyron V2

Let’s delve into the specs that make the Veyron V2 stand out. With a 3.6 GHz fifteen wide, aggressive out-of-order pipeline, and 32 cores per cluster, scalability is a breeze—up to 192 cores, to be exact. Add to that a generous 128 MB of shared L3 cache per cluster and a 512b vector unit, and you’ve got yourself a processor that doesn’t just perform, it excels.

For those interested in AI, the Veyron V2 comes equipped with Ventana AI matrix extensions, server-class IOMMU, and Advanced Interrupt Architecture (AIA) system IP. Additionally, advanced mitigations for side channel attacks and comprehensive RAS features ensure that performance is not only top-tier but also secure.

Features of the Veyron V2

  • Fifteen wide, aggressive out-of-order pipeline
  • 3.6 GHz
  • 4 nm process technology
  • 32 cores per cluster
  • High core count multi-cluster scalability up to 192 cores
  • 128 MB of shared L3 cache per cluster
  • 512b vector unit
  • Ventana AI matrix extensions
  • Provided with server-class IOMMU and Advanced Interrupt Architecture (AIA) system IP
  • Advanced side channel attack mitigations
  • Comprehensive RAS features
  • Top-down performance tuning methodology
  • SDK released with necessary software already ported to Veyron
  • Veyron V2 Development Platform available

Software developers will find the provided SDK—a comprehensive set of software tools already proven on Ventana’s RISC-V platform—exceptionally useful. It simplifies the transition to Veyron, ensuring that software is already ported and ready to harness the full potential of the processor.

Ventana’s Veyron V2 is setting a new standard for RISC-V processors, and those interested should not miss the detailed technical presentation by Greg Favor, CTO of Ventana, at the RISC-V Summit North America 2023. It’s evident that this processor is poised to make a significant impact in the tech industry, offering unparalleled performance and efficiency that aligns with the needs of modern data centers, automotive, 5G, AI, and client applications.

Source : Ventana

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Synopsys unveils innovative RISC-V ARC-V processor IP for next-gen chip design

Synopsys unveils innovative RISC-V ARC-V processor IP for next-gen chip design

If you’re closely following the semiconductor space, you will be pleased to know that Synopsys, Inc. has made a significant announcement this week. With the introduction of the new RISC-V ARC-V Processor IP, a move set to empower customers with a gamut of processor choices tailored for optimal power-performance efficiency across various applications.

For the uninitiated, RISC-V is an open standard for processors that’s been gaining traction in the tech world, thanks to its flexibility and community-driven development. Synopsys’ foray into this area isn’t a simple step but a giant leap, building upon its decades-long prowess in processor IP and software toolkit development. The ARC-V Processor IP is the company’s existing ARC Processors’ latest incarnation, only supercharged with the perks of the RISC-V’s burgeoning software ecosystem.

RISC-V ARC-V processor IP

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Here’s what sets the ARC-V Processor IP apart:

  • High-performance, mid-range, and ultra-low power options: Tailor your chip’s energy consumption and processing power to your application’s demands.
  • Functional safety versions: These are designed to meet the rigorous demands of applications requiring a high level of reliability, such as automotive systems.
  • Synopsys MetaWare Development Toolkit: This toolkit stands out for producing highly efficient code, crucial for getting the most out of the processors.
  • Synopsys.ai: Integrated with the EDA suite, this offering is co-optimized with ARC-V Processor IP to streamline development and verification, enhancing productivity and results.

Industry experts and market leaders have already voiced their support for this innovation. Thomas Boehm from Infineon highlighted the importance of resilience in the automotive chip market and welcomed the addition of safety-certified RISC-V based processor IP. Similarly, Calista Redmond of RISC-V International lauded the move, noting Synopsys’ contribution to the flexibility and choice in the semiconductor ecosystem.

“The increasing numbers of chips in automotive systems demand resilience in the semiconductor ecosystem, and to that end the industry is pushing for the adoption of open standards like RISC-V,” said Thomas Boehm, senior vice president, Automotive Microcontroller at Infineon. “By developing safety-certified RISC-V based processor IP, Synopsys is supporting us to expand the architecture choices with an open standard to build high-performance automotive systems with the highest levels of functional safety, and we look forward to continuing to partner with them in our future products.”

Synopsys isn’t just about processor IP; its portfolio is a testimony to its ability to deliver power-efficient, scalable processors, already a staple in countless automotive, storage, and IoT systems. The ARC-V IP capitalizes on this legacy, offering ultra-configurable, extensible processors that allow developers to fine-tune their SoCs for the optimal balance of power, performance, and area (PPA).

The company’s commitment to RISC-V doesn’t end with product development. They’re actively participating in shaping the future of computing as part of the RISC-V International Board of Directors and Technical Steering Committee.

As for the nitty-gritty details, the ARC-V Processor IP lineup is quite robust:

  • Functional Safety (FS) Processor IP: Comes with integrated hardware safety features, supporting ASIL B and D safety levels, and facilitating automotive safety and cybersecurity qualifications.
  • ISO 9001-certified Quality Management System (QMS): Assures that the development standards meet the stringent ASIL D criteria.

If you are wondering how Synopsys supports the design and verification of SoCs using this new IP, look no further. Their portfolio includes Synopsys.ai, Fusion QuickStart Implementation Kits, and a suite of verification solutions that provide a comprehensive environment for system-level analysis, power and performance optimization, and accelerated software development.

The grand unveiling of the Synopsys ARC-V Processor IP portfolio has stirred the industry, with general availability kicking off in 2024. The lineup includes the 32-bit Synopsys ARC-V RMX, the 32-bit ARC-V RHX, and the 64-bit ARC-V RPX, catering to embedded, real-time, and host processing needs, respectively.

As we wrap up this exploration into Synopsys’ latest offering, it’s clear that the company is positioning itself as a key player in the RISC-V landscape. With these developments, Synopsys not only promises to deliver robust processor solutions but also signals its commitment to the open-source ecosystem, paving the way for innovation and choice in chip design.

Source: Synopsys

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New BeagleV-Fire FPGA and RISC-V Single Board Computer

New BeagleV-Fire FPGA and RISC-V Single Board Computer

BeagleBoard, a prominent player in the field of single-board computers (SBCs), has recently unveiled its latest product, the BeagleV-Fire. This advanced SBC is powered by Microchip’s PolarFire MPFS025T FCVG484E, a 5x core RISC-V System on Chip (SoC) that includes an integrated FPGA fabric. The BeagleV-Fire is the latest addition to the BeagleV series of SBCs, marking a significant step towards making computer architecture more accessible and encouraging open-source hardware development.

The BeagleV-Fire SBC has been thoughtfully designed to accommodate a wide range of applications. These include Internet of Things (IoT) devices, robotics, artificial intelligence (AI), and embedded systems. It utilizes the RISC-V instruction set architecture (ISA), an open-source hardware instruction set that allows for increased customization and flexibility in system design.

BeagleV-Fire FPGA and RISC-V layout

Moreover, the BeagleV-Fire incorporates FPGA fabric, a versatile technology that enables the creation of custom digital circuits. This combination of RISC-V SoC and FPGA fabric provides a high level of customization, making the BeagleV-Fire a useful tool for developers and enthusiasts.

BeagleV-Fire RISC-V SBC

The BeagleV-Fire SBC features a RISC-V CPU, which offers a high-performance, energy-efficient solution for processing tasks. It also includes a variety of memory options, such as eMMC, LPDDR4 RAM, and a microSD card socket, providing ample storage and memory capacity for various applications.

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In terms of networking and connectivity, the BeagleV-Fire offers Gigabit Ethernet, M.2 Key E, and a WiFi module. It also includes USB Type-C and Serial debug connectivity options. For expansion, the board includes a SYZYGY interface, a CSI connector, and cape header pins, allowing a wide range of add-on boards to be connected.

The BeagleV-Fire is designed with an open-source hardware approach, promoting collaboration and innovation within the technology community. It is also compatible with Linux systems, specifically Ubuntu, further enhancing its versatility and user-friendliness.

The BeagleV-Fire is powered by Microchip’s PolarFire FPGA SoC IC, a key component that enables asymmetric processing, energy efficiency, and security and reliability for intelligent edge applications. This combination of the PolarFire FPGA SoC IC and the RISC-V architecture creates new opportunities for innovation within the open-source community.

Availability and Pricing

The BeagleV-Fire is expected to make a significant impact in the world of SBCs and is now available priced at $150. The BeagleV-Fire aims to bring a new level of power, flexibility, and open-source collaboration to the world of single-board computers.

The BeagleV-Fire represents a noteworthy advancement in the field of SBCs. With its powerful RISC-V CPU, FPGA fabric, and a host of other features, it offers a versatile platform for a wide range of applications. Its open-source design and Linux compatibility further enhance its appeal, making it a promising tool for developers, hobbyists, and technology enthusiasts. The BeagleV-Fire is poised to make a significant contribution to the landscape of single-board computers, fostering a new era of innovation and collaboration.

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Qualcomm RISC-V Wear OS wearable platform

Qualcomm RISC-V Wear OS wearable platform

Qualcomm has announced that it is currently developing a RISC-V based wearables solution intended for use with Wear OS by Google. This development is a testament to Qualcomm’s innovative spirit and its commitment to fostering collaborations that drive technological advancements. The company’s ongoing collaboration with Google is a strategic move to enable a broader range of products within the ecosystem to benefit from custom CPUs that are both low power and high performance.

Qualcomm’s venture into RISC-V based wearables does not mean it will abandon its successful Snapdragon Wear platforms. These platforms have been the leading smartwatch silicon provider for the Wear OS ecosystem, and Qualcomm plans to continue investing in them. The company’s decision to explore RISC-V based wearables while simultaneously nurturing its Snapdragon Wear platforms is indicative of its strategy to diversify and strengthen its product offerings.

Snapdragon Wear

“The Snapdragon Wear platforms are made to deliver low-power, high-impact performance for a wide range of wearables, including smartwatches, kids’ watches, smart trackers and more. Depend on our Snapdragon Wear platforms to build stylish, functional wearables that are designed to deliver super-fast performance, extended battery life, always-on experiences, and always-connected usage.”

Wear OS by Google

In a recent development, both Qualcomm and Google have joined other industry leaders to launch the RISC-V Software Ecosystem (RISE). This move underscores their commitment to promoting open-source technologies and fostering a community of innovation and collaboration. RISE is expected to be a significant contributor to the advancement of RISC-V technology.

Moreover, Qualcomm is not limiting its investment in RISC-V technology to software alone. The company is also investing in a new venture to advance RISC-V hardware development. This investment is a clear signal of Qualcomm’s belief in the potential of RISC-V technology and its intention to be at the forefront of its evolution.

RISC-V, an open-source instruction set architecture (ISA), is a technology that allows any company to develop completely custom cores. This open-source nature of RISC-V encourages innovation and competition in the marketplace, leading to more robust and diverse product offerings. The freedom to customize cores can lead to the development of products that are tailored to specific needs and applications, potentially revolutionizing various sectors, including the wearables market.

As for the commercial product launch of the RISC-V wearable based solution, Qualcomm has stated that it will be announced at a later date. This announcement is eagerly anticipated by the industry, as it marks a significant milestone in the evolution of wearable technology.

Qualcomm’s venture into RISC-V based wearables represents a significant step forward in the wearable technology industry. By leveraging the open-source nature of RISC-V, Qualcomm is paving the way for more innovative, powerful, and efficient wearable devices. While the commercial product launch is yet to be announced, the industry is already abuzz with excitement about the potential of this new technology. Qualcomm’s commitment to investing in both its Snapdragon Wear platforms and RISC-V technology demonstrates its dedication to driving innovation and delivering superior product offerings to the Wear OS ecosystem.

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